Split gate non-volatile memory devices are well known in the art. For example, U.S. Pat. No. 7,927,994 discloses a split gate non-volatile memory cell. FIG. 1 illustrates an example of such a split gate memory cell formed on a semiconductor substrate 12. Source and drain regions 16 and 14 are formed as diffusion regions in substrate 12, and define a channel region 18 there between. The memory cell includes four conductive gates: a floating gate 22 disposed over and insulated from a first portion of the channel region 18 and a portion of the source region 16, a control gate 26 disposed over and insulated from the floating gate 22, an erase gate 24 disposed over and insulated from the source region 16, and a select gate 20 disposed over and insulated from a second portion of the channel region 18. A conductive contact 10 can be formed to electrically connect to the drain region 14. Because the channel region is formed along the planar surface of the semiconductor substrate, as device geometries get smaller, so too does total area (e.g. width) of the channel region. This reduces the current flow between the source and drain regions, requiring more sensitive sense amplifiers etc. to detect the state of the memory cell.
Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed. In a Fin-FET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has two side surfaces terminating in a top surface. Current from the source to the drain regions can then flow along the two side surfaces and the top surface. Thus, the width of the channel region is increased, thereby increasing the current flow. However, the width of the channel region is increased without sacrificing more semiconductor real estate by “folding” the channel region into two side surfaces and the top surface, thereby reducing the “footprint” of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed, where the floating gates are disposed adjacent to one of the side surfaces of the fin shaped member. Some examples of prior art Fin-FET non-volatile memory structures (although the number and configuration of the gates varies from the above described planar example in FIG. 1) include U.S. Pat. Nos. 7,423,310, 7,410,913 and 8,461,640, and U.S. Patent Publication 2017/0345840. It has also been proposed to form logic devices on fin shaped members. See for example U.S. Patent Publication 2017/0125429 and pending U.S. patent application Ser. No. 15/933,124.
However, these prior art Fin-FET structures have disclosed using the floating gate in stacked gate configuration, or using trapping material, or using SRO (silicon rich oxide) or using nanocrystal silicon to store charges, or other more complicated memory cell configurations.